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Integrated Circuit Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
FEATURES
* Sixteen differential LVDS outputs * CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL * Maximum output frequency: 700MHz * Translates any differential input signal (LVPECL, LVHSTL, SSTL, DCM) to LVDS levels without external bias networks * Translates any single-ended input signal to LVDS with resistor bias on nCLK input * Multiple output enable inputs for disabling unused outputs in reduced fanout applications * LVDS compatible * Output skew: 90ps (maximum) * Part-to-part skew: 500ps (maximum) * Propagation delay: 2.4ns (maximum) * Additive phase jitter, RMS: 148fs (typical) * 3.3V operating supply * 0C to 70C ambient operating temperature * Available in both standard and lead-free RoHS compliant packages
GENERAL DESCRIPTION
The ICS8516 is a low skew, high performance 1-to-16 Differential-to-LVDS Clock Distribution HiPerClockSTM Chip and a member of the HiPerClock S TM family of High Performance Clock Solutions from ICS. The ICS8516 CLK, nCLK pair can accept any differential input levels and translates them to 3.3V LVDS output levels. Utilizing Low Voltage Differential Signaling (LVDS), the ICS8516 provides a low power, low noise, pointto-point solution for distributing clock signals over controlled impedances of 100.
IC S
Dual output enable inputs allow the ICS8516 to be used in a 1-to-16 or 1-to-8 input/output mode. Guaranteed output and part-to-part skew specifications make the ICS8516 ideal for those applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK nCLK
PIN ASSIGNMENT
48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24
Q9 nQ9 Q8 nQ8 GND OE2 OE1 GND nQ7 Q7 nQ6 Q6
Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5 Q6 nQ6 Q7 nQ7
Q15 nQ15 Q14 nQ14 Q13 nQ13 Q12 nQ12 Q11 nQ11 Q10 nQ10 Q9 nQ9 Q8 nQ8
VDD nQ5 Q5 nQ4 Q4 VDD GND nQ3 Q3 nQ2 Q2 VDD
ICS8516
VDD nQ10 Q10 nQ11 Q11 VDD GND nQ12 Q12 nQ13 Q13 VDD
OE1 OE2
8516FY
48-Lead LQFP 7mm x 7mm x 1.4mm body package Y Package Top View
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nQ14 Q14 nQ15 Q15 GND CLK nCLK GND Q0 nQ0 Q1 nQ1
REV. B FEBRUARY 21, 2006
Integrated Circuit Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
Type Power Output Output Power Output Output Output Output Input Input Output Output Output Output Output Output Output Output Pullup Pulldown Description Positive supply pins. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Power supply ground. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Inver ting differential clock input. Non-inver ting differential clock input. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 6, 12, 25, 31, 36 2, 3 4, 5 7, 17, 20, 30, 41, 44 8, 9 10, 11 13, 14 15, 16 18 19 21, 22 23, 24 26, 27 28, 29 32, 33 34, 35 37, 38 39, 40 Name VDD nQ5, Q5 nQ4, Q4 GND nQ3, Q3 nQ2, Q2 nQ1, Q1 nQ0, Q0 nCLK CLK Q15, nQ15 Q14, nQ14 Q13, nQ13 Q12, nQ12 Q11, nQ11 Q10, nQ10 Q9, nQ9 Q8, nQ8
Differential output pair. LVDS interface levels. Output enable. OE2 controls outputs Q8, nQ8 thru Q15, nQ15; OE1 controls outputs Q0, nQ0 thru Q7, nQ7. 42, 43 OE2, OE1 Input Pullup LVCMOS/LVTTL interface levels. Differential output pair. LVDS interface levels. 45, 46 nQ7, Q7 Output 47, 48 nQ6, Q6 Output Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
8516FY
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REV. B FEBRUARY 21, 2006
Integrated Circuit Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
Test Conditions Minimum Typical 4 51 51 4 Maximum Units pF k k pF
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN CPD Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output)
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs OE1 0 1 0 1 OE2 0 0 1 1 Q0:Q7 Hi Z ACTIVE Hi Z ACTIVE nQ0:nQ7 Hi Z ACTIVE Hi Z ACTIVE Outputs Q8:Q15 Hi Z Hi Z ACTIVE ACTIVE nQ8:nQ15 Hi Z Hi Z ACTIVE ACTIVE
In the active mode, the state of the outputs are a function of the CLK and nCLK inputs as described in Table 3B.
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs CLK 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nCLK 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 Q0:Q15 LOW HIGH LOW HIGH HIGH LOW Outputs nQ0:nQ15 HIGH LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
8516FY
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REV. B FEBRUARY 21, 2006
Integrated Circuit Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
4.6V -0.5V to VDD + 0.5 V -0.5V to VDD + 0.5V 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO 70C
Symbol VDD IDD Parameter Positive Supply Voltage Static Power Supply Current RL = 100 No Load Test Conditions Minimum 3.135 Typical 3. 3 135 60 Maximum 3.465 16 5 75 Units V mA mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current OE1, OE2 OE1, OE2 OE1, OE2 OE1, OE2 VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V -150 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 5 Units V V A A
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO 70C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current CLK nCLK CLK nCLK Test Conditions VIN = VDD = 3.465V VIN = VDD = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 1.3 VDD - 0.85 Minimum Typical Maximum 150 5 Units A A A A V V
Peak-to-Peak Voltage 0.15 Common Mode Input Voltage; VCMR GND + 0.5 NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined ast VIH.
8516FY
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REV. B FEBRUARY 21, 2006
Integrated Circuit Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
Test Conditions Minimum 250 1.125 -10 -1 Typical 400 1.4 Maximum 600 50 1.6 50 +10 +1 -5.5 -12 Units mV mV V mV A A mA mA
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO 70C
Symbol VOD VOD VOS VOS IOZ IOFF IOSD IOS/IOSB Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change High Impedance Leakage Current Power Off Leakage Differential Output Shor t Circuit Current Output Shor t Circuit Current
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO 70C
Symbol fMAX tPD t sk(o) t sk(pp) t jit tR/tF odc tPZL, tPZH tPLZ, tPHZ Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Output Rise/Fall Time Output Duty Cycle Output Enable Time; NOTE 5 Output Disable Time; NOTE 5 Integration Range: 12kHz - 20MHz 20% to 80% 1.6 2.0 Test Conditions Minimum Typical Maximum 700 2. 4 90 500 148 100 45 50 55 0 55 5 5 Units MH z ns ps ps fs ps % ns ns
NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
8516FY
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REV. B FEBRUARY 21, 2006
Integrated Circuit Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a
-50 -60 -70 -80
ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 155.52MHz
(12kHz to 20MHz) = 148fs typical
SSB PHASE NOISE dBc/HZ
-90 -100
-100 -120 -130 -140 -150 -160 1k 10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated
above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment.
8516FY
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REV. B FEBRUARY 21, 2006
Integrated Circuit Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
PARAMETER MEASUREMENT INFORMATION
3.3V 5%
VDD
SCOPE
Qx
nCLK
Power Supply +
Float GND
-
LVDS
nQx
V
CLK
PP
Cross Points
V
CMR
GND
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx nQ nQy Qy
PART 1 nQx Qx PART 2 nQy Qy
tsk(o)
tsk(pp)
OUTPUT SKEW
PART-TO-PART SKEW
nCLK
80%
CLK nQ0:nQ15 Q0:Q15
tPD
80% VOD
Clock Outputs
20% tR tF
20%
PROPAGATION DELAY
8516FY
OUTPUT RISE/FALL TIME
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REV. B FEBRUARY 21, 2006
Integrated Circuit Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
VDD
nQ0:nQ15 Q0:Q15
out
t
PERIOD
odc =
t PW t PERIOD
out
x 100%
VOS/ VOS
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OFFSET VOLTAGE SETUP
VDD out
VDD out
DC Input
LVDS
100
VOD/ VOD out
DC Input
LVDS
out
DIFFERENTIAL OUTPUT VOLTAGE SETUP
DIFFERENTIAL OUTPUT SHORT
CIRCUIT
CURRENT SETUP
VDD
out IOS DC Input
LVDS
IOSB out
LVDS
IOFF
OUTPUT SHORT CIRCUIT CURRENT SETUP
8516FY
POWER OFF LEAKAGE SETUP
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REV. B FEBRUARY 21, 2006
t PW
DC Input
LVDS
IOSD
VDD
Integrated Circuit Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD= 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input
CLKx
V_REF
nCLKx
C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVDS - Like OUTPUT All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, we recommend that there is no trace attached.
8516FY
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REV. B FEBRUARY 21, 2006
Integrated Circuit Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 2A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVDS DRIVER
3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 125 R4 125 CLK Zo = 50 Ohm C2 nCLK HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 2E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER WITH AC COUPLE
8516FY
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REV. B FEBRUARY 21, 2006
Integrated Circuit Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs.
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 3. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the
3.3V 3.3V LVDS_Driver R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
HiPerClockS
FIGURE 3. TYPICAL LVDS DRIVER TERMINATION
SCHEMATIC EXAMPLE
Figure 4 shows a schematic example of ICS8516. In this example, the input is driven by an LVDS driver. For LVDS buffer, it is recommended to terminate the unused outputs for better signal integrity. The decoupling capacitors should be physically located near the power pin.
Zo = 50 Ohm + R16 100 Zo = 50 Ohm LVDS_input U1 8516 Zo = 50 Ohm Q6 nQ6 Q7 nQ7 GND OE1 OE2 GND nQ8 Q8 nQ9 Q9 VDD Q13 nQ13 Q12 nQ12 GND VDD Q11 nQ11 Q10 nQ10 VDD 48 47 46 45 44 43 42 41 40 39 38 37 + R10 100 Zo = 50 Ohm LVDS_input
VDD=3.3V
-
LVDS_Driver Zo = 50 Ohm
R17 100 Zo = 50 Ohm
13 14 15 16 17 18 19 20 21 22 23 24
nQ1 Q1 nQ0 Q0 GND nCLK CLK GND Q15 nQ15 Q14 nQ14
VDD Q2 nQ2 Q3 nQ3 GND VDD Q4 nQ4 Q5 nQ5 VDD
12 11 10 9 8 7 6 5 4 3 2 1
-
25 26 27 28 29 30 31 32 33 34 35 36
Zo = 50 Ohm + R1 100 Zo = 50 Ohm LVDS_input
-
(U1-1)
VDD=3.3V
(U1-6)
(U1-12)
(U1-25)
(U1-31)
(U1-36)
C1 0.1u
C2 0.1u
C3 0.1u
C4 0.1u
C5 0.1u
C6 0.1u
Decoupling capacitors located near the power pins
FIGURE 4. ICS8516 LVDS BUFFER SCHEMATIC EXAMPLE
8516FY
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REV. B FEBRUARY 21, 2006
Integrated Circuit Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
FOR
48 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 67.8C/W 47.9C/W 200 55.9C/W 42.1C/W 500 50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8516 is: 1821
8516FY
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REV. B FEBRUARY 21, 2006
Integrated Circuit Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
48 LEAD LQFP
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc
8516FY
BBC MINIMUM NOMINAL 48 -0.05 1.35 0.17 0.09 --1.40 0.22 -9.00 BASIC 7.00 BASIC 5.50 Ref. 9.00 BASIC 7.00 BASIC 5.50 Ref. 0.50 BASIC 0.45 0 -0.60 --0.75 7 0.08
REV. B FEBRUARY 21, 2006
MAXIMUM
1.60 0.15 1.45 0.27 0.20
Reference Document: JEDEC Publication 95, MS-026 www.icst.com/products/hiperclocks.html
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Integrated Circuit Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
Marking ICS8516FY ICS8516FY Package 48 Lead LQFP 48 Lead LQFP 48 Lead "Lead-Free" LQFP 48 Lead "Lead-Free" LQFP Shipping Packaging tray 1000 tape & reel tray 1000 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS8516FY ICS8516FYT ICS8516FYLF ICS8516FYLFT
ICS8516FYLF ICS8516FYLF
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8516FY
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REV. B FEBRUARY 21, 2006
Integrated Circuit Systems, Inc.
ICS8516
LOW SKEW, 1-TO-16 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
REVISION HISTORY SHEET
Rev A A A
Table T1 T1 T2 T8
B
T5
Page 2 8 2 3 9 12 1 5 6 9
Description of Change Pin Description table - added pins 47 thru 48. Added LVDS Driver Termination in the Application Information section. Pin Description Table - switched pin names for 45, 46 & 47,48 Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical. Updated Differential Clock Input Interface section. Ordering Information Table - added Lead-Free par t numbers. Feature Section - added Additive Phase Jitter bullet. AC Characteristics Table - added Additive Phase Jitter. Added Additive Phase Jitter section. Added Recommendations for Unused Input and Output Pins
Date 3/31/03 5/6/03 7/30/04
2/21/06
8516FY
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